A Game Changer for Next Generation of Electrical Intelligent Vehicles
Stephane Strahm, Kalray Product Marketing Manager explains heterogeneous multi-processing
New Intelligent Processors
Next vehicle generation will be Autonomous, Electrified and Connected. The Automotive industry is facing two major productization challenges in this regard. The first one is to address the always-growing need of performance to answer the ADAS (Advanced Driving Assistant System)/AD (Autonomous Driving) hungry computing power. The second one is to leverage the experience of the 20 past years: without the need to add yet-another ECU (Electronic Component Unit) for yet-another function.
Performance and aggregation of functions are the keys for upcoming autonomous vehicle production.
Addressing the main challenges: Perception and path planning
Looking at the performance needs, the finding is obvious. The perception modules are implementing capabilities to execute computer vision supported by machine learning. This relies on heavy calculations requiring dedicated mostly ‘integer’ accelerators providing exceptional frame per second per watt performance.
You can add the motion planning modules relying on mathematical algorithms (linear/non-linear algebra) providing optimized path options. Dedicated ‘floating point’ accelerators are ensuring required latency for safety.
The industry has been prototyping these systems for years. Beside the technology challenge, it is important to understand first the impacts that it is generating.
The Automotive industry is shifting gears
Car manufacturers are facing a giant market shift where their value is evolving. The ‘cars’ are becoming a medium for digital user experiences, service providers, as fleet elements. This impacts drastically the value chain, the branding, the marketing and even internal company organization. If you look at the last past five years, you see the changes in company’s vision statements, the eco-systems’ storm with competitors alliances (BMW/Daimler…), start-ups acquisitions (Cruise…), and full re-org’s (Delphi-Aptiv…).
But what the car manufacturers need to learn from the last 20 years is that they need to get back in control of their system. The traditional Tier-1 black-box, adding an ECU for each new feature is no longer sustainable. The complexity of the E/E architecture has become unmanageable. We are seeing vehicles with more than 100 ECUs. With ADAS and AD, this number will grow further.
[SD1] Using traditional E/E architectures, it would not be possible to achieve the right level of performance and function integration required in the next generations of cars. It is the reason why car manufacturers, to meet these challenges, are reinventing their own systems by introducing zone or domain architectures and by favoring an aggregation of functions within ECU or actual processors. Aggregating functions requires the need to provide hardware capabilities to run diverse types of algorithms on a single CPU (Central Processing Unit).
Looking at these needs, the semi-conductor industry took the rapid approach of combining existing elements: a CPU for application, GPU (Graphics Processing Unit) for acceleration and a Microcontroller for safety. A very heterogeneous setup managed by a Software Hypervisor taking care of isolating functions and sharing resources. It does work but is very complex. The early developments with such solutions show complexity of programming, maintaining, validating and certifying.
If we take a step back, we are actually facing a typical industry approach: taking what exists at the time to quickly answer new use cases. Solving tomorrow’s problems with today’s combination of technologies is complicating designs.
For new use cases, the long-term view is to consider new optimized technology, new intelligent processors
MPPA®, a disruptive technology for applications performance and aggregation
Being able to combine different types of computing for application and acceleration within one electronic component, while ensuring that each of these computes are isolated from each other, is key.
This is what the Kalray’s Manycore architecture is providing. The MPPA®, Massively Parallel Processor Array, is a new intelligent processor providing 80 cores (CPU-type) coupled with 80 accelerators (AI-type/Math-type), grouped into clusters. Each cluster (a group of 16 cores/16 accelerators) can run independently thanks to a communication fabric ensuring isolation. The below graphic illustrates typical use case: integration of high-performance application using dedicated accelerators, with isolated command and control island.
The number of compute power units combined with the capability of parallelization of execution (core, cluster and chip level) provides the performance that can scale from AD Level 2 to 5.
The spatial isolation by hardware-design, ensured by architecture and configurable network-on-chip, provides freedom-from-interference without the need of a Software Hypervisor to reach ISO26262 ASIL-B level.
Change of paradigm: get prepared for long term production
System architects can now consider flexibility and scalability not only at ECU level but at component level. We are supporting all major OEM and Tier-1’s for scalable use cases by running multiple AI applications in one chip without interference, facilitating safety assessment. We are developing systems that isolate the control unit from the image processing acceleration, without the need for the software hypervisor.
Easy programmability with open standards
Kalray focus on enabling their customers long term production by providing typical development environments (C/C++) and open software standard API (Application Programming Interface) facilitating adoption, portability and maintenance. The typical integration problem is solved as each partner develops their own part of the chip, without interfering with others. With the MPPA®, you can rethink your overall architecture, reduce the complexity of programming, while maintaining and scaling your systems.